A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS
M. Raj, M. Monge and A. Emami, "A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS," 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015, pp. 1-4.
A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS
This paper describes an ultra-low-power VCSEL transmitter in 32nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. The resulting nonlinearity and loss in bandwidth is modelled and compensated by a nonlinear equalization technique. The time domain optical responses for “one” and “zero” bits are used to find the optimum equalization technique. The rising and falling edges were equalized separately and the equalization delay is selected based on the bias current of the VCSEL. The transmitter achieves energy efficiency of 0.77pJ/b at 20Gb/s.
